Testability Analysis

studio fattibilitàTestability analysys is an important step which , if introduced within the initial developing phase of PCB may be able to:

  • Drastically reduce testing time
  • Get more precise diagnostic indications
  • Achieve a grater reproducibility of your product
  • Attain higher quality standard

ICT test, mainly carried out to find manufacturing errors, (shorts, unsoldered pins, wrong , missing, inverted components , … etc…etc) has the characteristic of testing the component being able to virtually “isolate” it from the rest of the circuit. The degree of coverage of an ICT test is always board-dependant.

A complex digital board for example can reach a coverage level equal to about 97-98%.

To make this possible, it is necessary to take into consideration some basic rules to allow a good testability of the single components.

Here following some of the principal rules enforced by E.S. during TESTABILITY analysis of a board:

Provide a Test Point for every board net (Side to be contacted is preferably solder (bottom) side)  
Provide at least two Test Point for nets with low value resistors  (i.e. <10 ohm) so to allow more accurate Kelvin measurements
Provide more than two Test Points for Power and Ground net so to provide more connections for board power supply; this improves stability for tests that require the board being powered up. (and greatly improves complex digital test stability). 
Do not directly force reset or chip enable pins but always use pullups or pull down resistors

This allows to reset or disable easily the components during test when needed. Use of pull values of minimum 330Ohm is recommended. 

Avoid connecting together Reset  pins of components ( i.e. Micro reset with Flash reset….) Split the reset nets in more subnets wherever possible for example through 120 Ohm resistors.  
Always use oscillators provided with disable pin so to stop clocks when needed. Again, enable this pin through resistors and provide test point on disable
Wherever possible place test points also on unused output pins . This allows checking for shorts those pins that , although unused, if shorted could give rise to damage to the component later in the field.
In case of complex components choose (wherever possible) Boundary Scan enabled components. This allows an accurate in circuit test through a standard test methodology. Very complex components can be verified this way by means of their internal BS chain using simple built-in test instructions.